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sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 1 post office box 655303 ? dallas, texas 75265 members of the texas instruments scope ? family of testability products octal test-integrated circuits functionally equivalent to 'f244 and 'bct244 in the normal-function mode compatible with the ieee standard 1149.1-1990 (jtag) test access port and boundary-scan architecture test operation synchronous to test access port (tap) implement optional test reset signal by recognizing a double-high-level voltage (10 v ) on tms pin scope ? instruction set ieee standard 1149.1-1990 required instructions, optional intest, clamp and highz parallel-signature analysis at inputs pseudo-random pattern generation from outputs sample inputs/toggle outputs package options include plastic small-outline (dw) packages, ceramic chip carriers (fk), and standard plastic and ceramic 300-mil dips (jt, nt) description the 'bct8244a scan test devices with octal buffers are members of the texas instruments scope ? testability integrated-circuit family. this family of devices supports ieee standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. scan access to the test circuitry is accomplished via the 4-wire test access port (tap) interface. in the normal mode, these devices are functionally equivalent to the 'f244 and 'bct244 octal buffers. the test circuitry can be activated by the tap to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. activating the tap in normal mode does not affect the functional operation of the scope ? octal buffers. in the test mode, the normal operation of the scope ? octal buffers is inhibited and the test circuitry is enabled to observe and control the i/o boundary of the device. when enabled, the test circuitry can perform boundary-scan test operations, as described in ieee standard 1149.1-1990. copyright ? 1996, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. scope is a trademark of texas instruments incorporated. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1oe 1y1 1y2 1y3 1y4 gnd 2y1 2y2 2y3 2y4 tdo tms 2oe 1a1 1a2 1a3 1a4 2a1 v cc 2a2 2a3 2a4 tdi tck sn54bct8244a . . . jt package sn74bct8244a ... dw or nt p ackage (top view) 3212827 12 13 5 6 7 8 9 10 11 25 24 23 22 21 20 19 2a4 tdi tck nc tms tdo 2y4 1a2 1a1 2oe nc 1oe 1y1 1y2 426 14 15 16 17 18 1y3 1y4 gnd nc 2y1 2y2 2y3 1a3 1a4 2a1 nc v 2a2 2a3 sn54bct8244a . . . fk package (top view) nc no internal connection cc on products compliant to mil-prf-38535, all parameters are tested unless otherwise noted. on all other products, production processing does not necessarily include testing of all parameters.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 2 post office box 655303 ? dallas, texas 75265 description (continued) four dedicated test terminals control the operation of the test circuitry: test data input (tdi), test data output (tdo), test mode select (tms), and test clock (tck). additionally, the test circuitry performs other testing functions such as parallel-signature analysis (psa) on data inputs and pseudo-random pattern generation (prpg) from data outputs. all testing and scan operations are synchronized to the tap interface. the sn54bct8244a is characterized for operation over the full military temperature range of 55 c to 125 c. the sn74bct8244a is characterized for operation from 0 c to 70 c. function table (normal mode, each buffer) inputs output oe a y h x z l ll l h h logic symbol 2 scan 'bct8244a 23 1a1 1y1 2 tdi 14 tdi tck-in en1 1 22 1a2 1y2 3 tms 12 tms 13 tck en2 24 tck-out 21 1a3 1y3 4 20 1a4 1y4 5 19 2a1 2y1 7 17 2a2 2y2 8 16 2a3 2y3 9 15 2a4 2y4 10 2oe 1oe f 1 2 tdo 11 tdo 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. pin numbers shown are for the dw, jt, and nt packages.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 3 post office box 655303 ? dallas, texas 75265 functional block diagram boundary- control register bypass register boundary-scan register instruction register tdi tms tck tdo tap controller v cc v cc 1oe 1a1 v cc v cc v cc v cc one of four channels 2oe 2a1 v cc v cc one of four channels 1 23 24 19 14 12 13 2y1 1y1 2 7 11 pin numbers shown are for the dw, jt, and nt packages.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal name description 1a11a4, 2a12a4 normal-function data inputs. see function table for normal-mode logic. internal pullups force these inputs high if left unconnected. gnd ground 1oe , 2oe normal-function output-enable inputs. see function table for normal-mode logic. internal pullups force these inputs high if left unconnected. tck test clock. one of four terminals required by ieee standard 1149.1-1990. test operations of the device are synchronous to tck. data is captured on the rising edge of tck and outputs change on the falling edge of tck. an internal pullup forces tck to a high level if left unconnected. tdi test data input. one of four terminals required by ieee standard 1149.1-1990. tdi is the serial input for shifting data through the instruction register or selected data register. an internal pullup forces tdi to a high level if left unconnected. tdo test data output. one of four terminals required by ieee standard 1149.1-1990. tdo is the serial output for shifting data through the instruction register or selected data register. an internal pullup forces tdo to a high level when it is not active and is not driven from an external source. tms test mode select. one of four terminals required by ieee standard 1149.1-1990. tms directs the device through its tap controller states. an internal pullup forces tms to a high level if left unconnected. tms also provides the optional test reset signal of ieee standard 1149.1-1990. this is implemented by recognizing a third logic level, double high (v ihh ), at tms. v cc supply voltage 1y11y4, 2y12y4 normal-function data outputs. see function table for normal-mode logic.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 5 post office box 655303 ? dallas, texas 75265 test architecture serial-test information is conveyed by means of a 4-wire test bus, or tap, that conforms to ieee standard 1149.1-1990. test instructions, test data, and test control signals all are passed along this serial-test bus. the tap controller monitors two signals from the test bus, tck and tms. the tap controller extracts the synchronization (tck) and state control (tms) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. figure 1 shows the tap-controller state diagram. the tap controller is fully synchronous to the tck signal. input data is captured on the rising edge of tck, and output data changes on the falling edge of tck. this scheme ensures that data to be captured is valid for fully one-half of the tck cycle. the functional block diagram shows the ieee standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the tap controller, and the test registers. as shown, the device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a 2-bit boundary-control register, and a 1-bit bypass register. test-logic-reset run-test /idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr update-dr tms = l tms = l tms = h tms = l tms = h tms = h tms = l tms = h tms = l tms = l tms = h tms = l exit2-dr select-ir-scan capture-ir shift-ir exit1-ir pause-ir update-ir tms = l tms = l tms = h tms = l tms = h tms = h tms = l tms = h tms = l exit2-ir tms = l tms = h tms = h tms = h tms = l tms = h tms = l tms = h tms = h tms = h tms = l figure 1. tap-controller state diagram
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 6 post office box 655303 ? dallas, texas 75265 state diagram description the tap controller is a synchronous finite state machine that provides test control signals throughout the device. the state diagram shown in figure 1 is in accordance with ieee standard 1149.1-1990. the tap controller proceeds through its states based on the level of tms at the rising edge of tck. as shown, the tap controller consists of 16 states. there are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. a stable state is a state the tap controller can retain for consecutive tck cycles. any state that does not meet this criterion is an unstable state. there are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. only one register can be accessed at a time. test-logic-reset the device powers up in the test-logic-reset state. in the stable test-logic-reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. the instruction register is reset to an opcode that selects the optional idcode instruction, if supported, or the bypass instruction. certain data registers also can be reset to their power-up values. the state machine is constructed such that the tap controller returns to the test-logic-reset state in no more than five tck cycles if tms is left high. the tms pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. for the 'bct8244a, the instruction register is reset to the binary value 1 1111111, which selects the bypass instruction. the boundary-control register is reset to the binary value 10, which selects the psa test operation. run-test / idle the tap controller must pass through the run-test/idle state (from test-logic-reset) before executing any test operations. the run-test/idle state also can be entered following data-register or instruction-register scans. run-test/idle is a stable state in which the test logic may be actively running a test or may be idle. the test operations selected by the boundary-control register are performed while the tap controller is in the run-test/idle state. select-dr-scan, select-lr-scan no specific function is performed in the select-dr-scan and select-lr-scan states, and the tap controller exits either of these states on the next tck cycle. these states allow the selection of either data-register scan or instruction-register scan. capture-dr when a data-register scan is selected, the tap controller must pass through the capture-dr state. in the capture-dr state, the selected data register may capture a data value as specified by the current instruction. such capture operations occur on the rising edge of tck, upon which the tap controller exits the capture-dr state. shift-dr upon entry to the shift-dr state, the data register is placed in the scan path between tdi and tdo and, on the first falling edge of tck, tdo goes from the high-impedance state to an active state. tdo enables to the logic level present in the least-significant bit of the selected data register. while in the stable shift-dr state, data is serially shifted through the selected data register on each tck cycle. the first shift occurs on the first rising edge of tck after entry to the shift-dr state (i.e., no shifting occurs during the tck cycle in which the tap controller changes from capture-dr to shift-dr or from exit2-dr to shift-dr). the last shift occurs on the rising edge of tck, upon which the tap controller exits the shift-dr state.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 7 post office box 655303 ? dallas, texas 75265 exit1-dr, exit2-dr the exit1-dr and exit2-dr states are temporary states that end a data-register scan. it is possible to return to the shift-dr state from either exit1-dr or exit2-dr without recapturing the data register. on the first falling edge of tck after entry to exit1-dr, tdo goes from the active state to the high-impedance state. pause-dr no specific function is performed in the stable pause-dr state, in which the tap controller can remain indefinitely. the pause-dr state suspends and resumes data-register scan operations without loss of data. update-dr if the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of tck, following entry to the update-dr state. capture-ir when an instruction-register scan is selected, the tap controller must pass through the capture-ir state. in the capture-ir state, the instruction register captures its current status value. this capture operation occurs on the rising edge of tck, upon which the tap controller exits the capture-ir state. for the 'bct8244a, the status value loaded in the capture-ir state is the fixed binary value 10000001. shift-ir upon entry to the shift-ir state, the instruction register is placed in the scan path between tdi and tdo and, on the first falling edge of tck, tdo goes from the high-impedance state to an active state. tdo enables to the logic level present in the least-significant bit of the instruction register. while in the stable shift-ir state, instruction data is serially shifted through the instruction register on each tck cycle. the first shift occurs on the first rising edge of tck after entry to the shift-ir state (i.e., no shifting occurs during the tck cycle in which the tap controller changes from capture-ir to shift-ir or from exit2-ir to shift-ir). the last shift occurs on the rising edge of tck, upon which the tap controller exits the shift-ir state. exit1-ir, exit2-ir the exit1-ir and exit2-ir states are temporary states that end an instruction-register scan. it is possible to return to the shift-ir state from either exit1-ir or exit2-ir without recapturing the instruction register. on the first falling edge of tck after entry to exit1-ir, tdo goes from the active state to the high-impedance state. pause-ir no specific function is performed in the stable pause-ir state, in which the tap controller can remain indefinitely. the pause-ir state suspends and resumes instruction-register scan operations without loss of data. update-ir the current instruction is updated and takes effect on the falling edge of tck, following entry to the update-ir state.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 8 post office box 655303 ? dallas, texas 75265 register overview with the exception of the bypass register, any test register may be thought of as a serial-shift register with a shadow latch on each bit. the bypass register differs in that it contains only a shift register. during the appropriate capture state (capture-ir for instruction register, capture-dr for data registers), the shift register may be parallel loaded from a source specified by the current instruction. during the appropriate shift state (shift-ir or shift-dr), the contents of the shift register are shifted out from tdo while new contents are shifted in at tdi. during the appropriate update state (update-ir or update-dr), the shadow latches are updated from the shift register. instruction register description the instruction register (ir) is eight bits long and tells the device what instruction is to be executed. information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during capture-dr. table 2 lists the instructions supported by the 'bct8244a. the even-parity feature specified for scope ? devices is not supported in this device. bit 7 of the instruction opcode is a don't-care bit. any instructions that are defined for scope ? devices but are not supported by this device default to bypass. during capture-ir, the ir captures the binary value 10000001. as an instruction is shifted in, this value is shifted out via tdo and can be inspected as verification that the ir is in the scan path. during update-ir, the value that has been shifted into the ir is loaded into shadow latches. at this time, the current instruction is updated and any specified mode change takes effect. at power up or in the test-logic-reset state, the ir is reset to the binary value 1 1111111, which selects the bypass instruction. the ir order of scan is shown in figure 2. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 tdo tdi bit 7 (msb) don't care bit 0 (lsb) figure 2. instruction register order of scan data register description boundary-scan register the boundary-scan register (bsr) is 18 bits long. it contains one boundary-scan cell (bsc) for each normal-function input pin and one bsc for each normal-function output pin. the bsr is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input terminals. the source of data to be captured into the bsr during capture-dr is determined by the current instruction. the contents of the bsr may change during run-test/idle as determined by the current instruction. the contents of the bsr are not changed in test-logic-reset. the bsr order of scan is from tdi through bits 170 to tdo. table 1 shows the bsr bits and their associated device pin signals.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 9 post office box 655303 ? dallas, texas 75265 table 1. boundary-scan register configuration bsr bit number device signal bsr bit number device signal bsr bit number device signal 17 1oe 15 1a1 7 1y1 16 2oe 14 1a2 6 1y2 13 1a3 5 1y3 12 1a4 4 1y4 11 2a1 3 2y1 10 2a2 2 2y2 9 2a3 1 2y3 8 2a4 0 2y4 boundary-control register the boundary-control register (bcr) is two bits long. the bcr is used in the context of the runt instruction to implement additional test operations not included in the basic scope ? instruction set. such operations include prpg and psa. table 3 shows the test operations that are decoded by the bcr. during capture-dr, the contents of the bcr are not changed. at power up or in test-logic-reset, the bcr is reset to the binary value 10, which selects the psa test operation. the bcr order of scan is shown in figure 3. tdo tdi bit 1 (msb) bit 0 (lsb) figure 3. boundary-control register order of scan bypass register the bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation. during capture-dr, the bypass register captures a logic 0. the bypass register order of scan is shown in figure 4. bit 0 tdo tdi figure 4. bypass register order of scan
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 10 post office box 655303 ? dallas, texas 75265 instruction-register opcode description the instruction-register opcodes are shown in table 2. the following descriptions detail the operation of each instruction. table 2. instruction-register opcodes binary code 2 bit 7 bit 0 msb lsb scope opcode description selected data register mode x0000000 extest/intest boundary scan boundary scan test x0000001 bypass 3 bypass scan bypass normal x0000010 sample/preload sample boundary boundary scan normal x0000011 intest/extest boundary scan boundary scan test x0000100 bypass 3 bypass scan bypass normal x0000101 bypass 3 bypass scan bypass normal x0000110 highz (tribyp) control boundary to high impedance bypass modified test x0000111 clamp (setbyp) control boundary to 1/0 bypass test x0001000 bypass 3 bypass scan bypass normal x0001001 runt boundary run test bypass test x0001010 readbn boundary read boundary scan normal x0001011 readbt boundary read boundary scan test x0001100 celltst boundary self test boundary scan normal x0001101 tophip boundary toggle outputs bypass test x0001110 scancn boundary-control register scan boundary control normal x0001111 scanct boundary-control register scan boundary control test all others bypass bypass scan bypass normal 2 bit 7 is a don't-care bit; x = don't care. 3 the bypass instruction is executed in lieu of a scope ? instruction that is not supported in the 'bct8244a. boundary scan this instruction conforms to the ieee standard 1149.1-1990 extest and intest instructions. the bsr is selected in the scan path. data appearing at the device input terminals is captured in the input bscs, while data appearing at the outputs of the normal on-chip logic is captured in the output bscs. data that has been scanned into the input bscs is applied to the inputs of the normal on-chip logic, while data that has been scanned into the output bscs is applied to the device output terminals. the device operates in the test mode. bypass scan this instruction conforms to the ieee standard 1149.1-1990 bypass instruction. the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. the device operates in the normal mode. sample boundary this instruction conforms to the ieee standard 1149.1-1990 sample/preload instruction. the bsr is selected in the scan path. data appearing at the device input terminals is captured in the input bscs, while data appearing at the outputs of the normal on-chip logic is captured in the output bscs. the device operates in the normal mode.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 11 post office box 655303 ? dallas, texas 75265 control boundary to high impedance this instruction conforms to the ieee standard 1149.1a-1993 highz instruction. the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. the device operates in a modified test mode in which all device output terminals are placed in the high-impedance state, the device input terminals remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 this instruction conforms to the ieee standard 1149.1a-1993 clamp instruction. the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. data in the input bscs is applied to the inputs of the normal on-chip logic, while data in the output bscs is applied to the device output terminals. the device operates in the test mode. boundary run test the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. the device operates in the test mode. the test operation specified in the bcr is executed during run-test/idle. the four test operations decoded by the bcr are: sample inputs/toggle outputs (topsip), prpg, psa, and simultaneous psa and prpg (psa/prpg). boundary read the bsr is selected in the scan path. the value in the bsr remains unchanged during capture-dr. this instruction is useful for inspecting data after a psa operation. boundary self test the bsr is selected in the scan path. all bscs capture the inverse of their current values during capture-dr. in this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and shadow-latch elements of the bsr. the device operates in the normal mode. boundary toggle outputs the bypass register is selected in the scan path. a logic 0 value is captured in the bypass register during capture-dr. data in the shift register elements of the selected output bscs is toggled on each rising edge of tck in run-test/idle and is then updated in the shadow latches and applied to the associated device output terminals on each falling edge of tck in run-test/idle. data in the selected input bscs remains constant and is applied to the inputs of the normal on-chip logic. data appearing at the device input terminals is not captured in the input bscs. the device operates in the test mode. boundary-control-register scan the bcr is selected in the scan path. the value in the bcr remains unchanged during capture-dr. this operation must be performed before a boundary-run test operation to specify which test operation is to be executed.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 12 post office box 655303 ? dallas, texas 75265 boundary-control register opcode description the bcr opcodes are decoded from bcr bits 10, as shown in table 3. the selected test operation is performed while the runt instruction is executed in the run-test/idle state. the following descriptions detail the operation of each bcr instruction and show the associated psa and prpg algorithms. table 3. boundary-control register opcodes binary code bit 1 bit 0 msb lsb description 00 sample inputs/toggle outputs (topsip) 01 pseudo-random pattern generation / 16-bit mode (prpg) 10 parallel-signature analysis/16-bit mode (psa) 11 simultaneous psa and prpg/8-bit mode (psa/prpg) it should be noted, in general, that while the control input bscs (bits 1716) are not included in the sample, toggle, psa, or prpg algorithms, the output-enable bscs (bits 1716 of the bsr) do control the drive state (active or high impedance) of the selected device output terminals. sample inputs / toggle outputs (topsip) data appearing at the device input terminals is captured in the shift-register elements of the input bscs on each rising edge of tck. this data is then updated in the shadow latches of the input bscs and applied to the inputs of the normal on-chip logic. data in the shift register elements of the output bscs is toggled on each rising edge of tck, updated in the shadow latches, and applied to the device output terminals on each falling edge of tck. pseudo-random pattern generation (prpg) a pseudo-random pattern is generated in the shift-register elements of the bscs on each rising edge of tck and then updated in the shadow latches and applied to the device output terminals on each falling edge of tck. this data also is updated in the shadow latches of the input bscs and applied to the inputs of the normal on-chip logic. figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are generated. an initial seed value should be scanned into the bsr before performing this operation. a seed value of all zeroes will not produce additional patterns. = 1a1 1y1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1y2 1y3 1y4 2y1 2y2 2y3 2y4 figure 5. 16-bit prpg configuration
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 13 post office box 655303 ? dallas, texas 75265 parallel-signature analysis (psa) data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register elements of the bscs on each rising edge of tck. this data is then updated in the shadow latches of the input bscs and applied to the inputs of the normal on-chip logic. data in the shadow latches of the output bscs remains constant and is applied to the device outputs. figure 6 shows the 16-bit linear-feedback shift-register algorithm through which the signature is generated. an initial seed value should be scanned into the bsr before performing this operation. = 1a1 1y1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1y2 1y3 1y4 2y1 2y2 2y3 2y4 = figure 6. 16-bit psa configuration simultaneous psa and prpg (psa / prpg) data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register elements of the input bscs on each rising edge of tck. this data is then updated in the shadow latches of the input bscs and applied to the inputs of the normal on-chip logic. at the same time, an 8-bit pseudo-random pattern is generated in the shift-register elements of the output bscs on each rising edge of tck, updated in the shadow latches, and applied to the device output terminals on each falling edge of tck. figure 7 shows the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. an initial seed value should be scanned into the bsr before performing this operation. a seed value of all zeroes will not produce additional patterns. = 1a1 1y1 1a2 1a3 1a4 2a1 2a2 2a3 2a4 1y2 1y3 1y4 2y1 2y2 2y3 2y4 = figure 7. 8-bit psa / prpg configuration
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 14 post office box 655303 ? dallas, texas 75265 timing description all test operations of the 'bct8244a are synchronous to tck. data on the tdi, tms, and normal-function inputs is captured on the rising edge of tck. data appears on the tdo and normal-function output terminals on the falling edge of tck. the tap controller is advanced through its states (as shown in figure 1) by changing the value of tms on the falling edge of tck and then applying a rising edge to tck. a simple timing example is shown in figure 8. in this example, the tap controller begins in the test-logic-reset state and is advanced through its states, as necessary, to perform one instruction-register scan and one data-register scan. while in the shift-ir and shift-dr states, tdi is used to input serial data and tdo is used to output serial data. the tap controller is then returned to the test-logic-reset state. table 4 details the operation of the test circuitry during each tck cycle. table 4. explanation of timing example tck cycle(s) tap state after tck description 1 test-logic-reset tms is changed to a logic 0 value on the falling edge of tck to begin advancing the tap controller toward the desired state. 2 run-test/idle 3 select-dr-scan 4 select-ir-scan 5 capture-ir the ir captures the 8-bit binary value 10000001 on the rising edge of tck as the tap controller exits the capture-ir state. 6 shift-ir tdo becomes active and tdi is made valid on the falling edge of tck. the first bit is shifted into the tap on the rising edge of tck as the tap controller advances to the next state. 713 shift-ir one bit is shifted into the ir on each tck rising edge. with tdi held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the ir. at the same time, the 8-bit binary value 10000001 is serially scanned out of the ir via tdo. in tck cycle 13, tms is changed to a logic 1 value to end the ir scan on the next tck cycle. the last bit of the instruction is shifted as the tap controller advances from shift-ir to exit1-ir. 14 exit1-ir tdo becomes inactive (goes to the high-impedance state) on the falling edge of tck. 15 update-ir the ir is updated with the new instruction (bypass) on the falling edge of tck. 16 select-dr-scan 17 capture-dr the bypass register captures a logic 0 value on the rising edge of tck as the tap controller exits the capture-dr state. 18 shift-dr tdo becomes active and tdi is made valid on the falling edge of tck. the first bit is shifted into the tap on the rising edge of tck as the tap controller advances to the next state. 1920 shift-dr the binary value 101 is shifted in via tdi, while the binary value 010 is shifted out via tdo. 21 exit1-dr tdo becomes inactive (goes to the high-impedance state) on the falling edge of tck. 22 update-dr in general, the selected data register is updated with the new data on the falling edge of tck. 23 select-dr-scan 24 select-ir-scan 25 test-logic-reset test operation completed
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 15 post office box 655303 ? dallas, texas 75265 ?????? ?????? ????? ????? ???????? ???????? ???????? ???????? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ????? ????? ?????? ?????? test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir update-ir select-dr-scan capture-dr shift-dr exit1-dr update-dr select-dr-scan select-ir-scan test-logic-reset tck tms tdi tdo ?? ?? tap controller state 3-state (tdo) or don't care (tdi) figure 8. timing example absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : except tms (see note 1) 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tms (see note 1) 0.5 v to 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the disabled or power-off state 0.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high state 0.5 v to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current into any output in the low state: sn54bct8244a (tdo) 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn54bct8244a (any y) 96 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn74bct8244a (tdo) 48 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sn74bct8244a (any y) 128 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum power dissipation at t a = 55 c (in still air) (see note 2): dw package 1.7 w . . . . . . . . . . . . . . . . . . nt package 1.3 w . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input voltage rating may be exceeded if the input clamp-current rating is observed. 2. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils, except for the nt package, which has a trace length of zero. for more information, refer to the package thermal considerations application note in the abt advanced bicmos technology data book , literature number scbd002.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 16 post office box 655303 ? dallas, texas 75265 recommended operating conditions sn54bct8244a sn74bct8244a unit min nom max min nom max unit v cc supply voltage 4.5 5 5.5 4.5 5 5.5 v v ih high-level input voltage 2 2 v v ihh double-high-level input voltage tms 10 12 10 12 v v il low-level input voltage 0.8 0.8 v i ik input clamp current 18 18 ma i oh high level out p ut current tdo 3 3 ma i oh high - le v el o u tp u t c u rrent any y 12 15 ma i ol low level out p ut current tdo 20 24 ma i ol lo w- le v el o u tp u t c u rrent any y 48 64 ma t a operating free-air temperature 55 125 0 70 c
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 17 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions sn54bct8244a sn74bct8244a unit parameter test conditions min typ 2 max min typ 2 max unit v ik v cc = 4.5 v, i i = 18 ma 1.2 1.2 v v cc = 4.75 v, i oh = 3 ma 2.7 3.4 2.7 3.4 any y i oh = 3 ma 2.4 3.4 2.4 3.4 an y y v cc = 4.5 v i oh = 12 ma 2 3.2 v oh i oh = 15 ma 2 3.1 v v cc = 4.75 v, i oh = 1 ma 2.7 3.4 2.7 3.4 tdo v cc =45v i oh = 1 ma 2.5 3.4 2.5 3.4 v cc = 4 . 5 v i oh = 3 ma 2.4 3.3 2.4 3.3 any y v cc =45v i ol = 48 ma 0.38 0.55 v ol an y y v cc = 4 . 5 v i ol = 64 ma 0.42 0.55 v v ol tdo v cc =45v i ol = 20 ma 0.3 0.5 v tdo v cc = 4 . 5 v i ol = 24 ma 0.35 0.5 i i v cc = 5.5 v, v i = 5.5 v 0.1 0.1 ma i ih v cc = 5.5 v, v i = 2.7 v 1 35 100 1 35 100 m a i ihh tms v cc = 5.5 v, v i = 10 v 1 1 ma i il v cc = 5.5 v, v i = 0.5 v 30 70 200 30 70 200 m a i ozh any y v cc =55v v o =27v 50 50 m a i ozh tdo v cc = 5 . 5 v , v o = 2 . 7 v 1 35 100 1 35 100 m a i ozl any y v cc =55v v o =05v 50 50 m a i ozl tdo v cc = 5 . 5 v , v o = 0 . 5 v 30 70 200 30 70 200 m a i ozpu v cc = 0 to 2 v, v o = 0.5 v or 2.7 v 250 250 m a i ozpd v cc = 2 v to 0, v o = 0.5 v or 2.7 v 250 250 m a i off v cc = 0, v i or v o 4.5 v 250 250 m a i os 3 v cc = 5.5 v, v o = 0 100 225 100 225 ma outputs high 3.5 7.5 3.5 7.5 i cc v cc = 5.5 v, outputs open outputs low 35 52 35 52 ma outputs disabled 1.5 3.5 1.5 3.5 c i v cc = 5 v, v i = 2.5 v or 0.5 v 10 10 pf c o v cc = 5 v, v o = 2.5 v or 0.5 v 18 18 pf 2 all typical values are at v cc = 5 v, t a = 25 c. 3 not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 18 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see figure 9) v cc = 5 v, t a = 25 c sn54bct8244a sn74bct8244a unit min max min max min max f clock clock frequency tck 0 20 0 20 0 20 mhz t pulse duration tck high or low 25 25 25 ns t w p u lse d u ration tms double high 50* 50* 50 ns any a before tck 6 6 6 t setu p time any oe before tck 6 6 6 ns t su set u p time tdi before tck 6 6 6 ns tms before tck 12 12 12 any a after tck 4.5 4.5 4.5 t h hold time any oe after tck 4.5 4.5 4.5 ns t h hold time tdi after tck 4.5 4.5 4.5 ns tms after tck 0 0 0 t d delay time power up to tck 100* 100* 100 ns * on products compliant to mil-prf-38535, this parameter is not production tested.
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 19 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see figure 9) parameter from (input) to (output) v cc = 5 v, t a = 25 c sn54bct8244a sn74bct8244a unit (input) (output) min typ max min max min max t plh a y 2 5.4 7 2 9 2 8.5 ns t phl a y 2 5.2 7 2 9 2 8.5 ns t pzh oe y 3 6 8 3 10 3 9.5 ns t pzl oe y 3.5 7 9 3.5 12 3.5 11 ns t phz oe y 2.5 6 8 2.5 10 2.5 9 ns t plz oe y 2.5 5.5 8 2.5 10 2.5 9 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see figure 9) parameter from (input) to (output) v cc = 5 v, t a = 25 c sn54bct8244a sn74bct8244a unit (input) (output) min typ max min max min max f max tck 20 20 20 mhz t plh tck ? M ? ?? M ??? M ? ?? ? ?? ??k ? M ??? ?? M ??? M ? ?? ? ?? ??k ?? ?? ??M ?? ?? ? ?? ? ?? ? ?? ??k ?? ?? ?? ?? ? ?? ?? ?? ? ?? ??k ? ?? ?M? ? ?? ? ?? ? ?? ? ?? ??k ? ?? ?? ?? ?? ? ?? ? ?? ? ?? ??k ? M? ? ?? M? ? M? ?? ?? ? ?? ??k ? ? ? ? ? ?M ? ? ?? ? ?? ??k ?? ?? ??M ?? ?? ??? ?? ?? ?? ? ?? ??k ?? ?? ?? ??? ??? ?? ? ?? ??k ? ? ?? ? ?? ?? ? ?? ??k ? ? ? ? ? ?? ? ?? ??k ? M ? ? M ? M ?? ?? ? ?? ??k ? M ? ?? M ? M ?? ?? ? ?? ??k ?? ??? ? ??? ?? ? ?? ??k ?? ?? ? ? ?? ?? ? ?? ??k ? ??? ?? ? ?? ?? ? ?? ??k ? ??? ?? ? ?? ??
sn54bct8244a, sn74bct8244a scan test devices with octal buffers scbs042e february 1990 revised july 1996 20 post office box 655303 ? dallas, texas 75265 parameter measurement information from output under test test point r1 c l (see note a) load circuit for totem-pole outputs load circuit for 3-state and open-collector outputs r1 s1 7 v (t pzl , t plz , o.c.) open (all others) from output under test test point r2 c l (see note a) r l = r1 = r2 1.5 v 1.5 v 1.5 v 3 v 3 v 0 v 0 v t h t su voltage waveforms setup and hold times timing input data input 1.5 v 1.5 v 3 v 3 v 0 v 0 v high-level pulse low-level pulse t w voltage waveforms pulse duration 1.5 v 1.5 v t phl t plh t plh t phl input out-of-phase output 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 3 v 0 v v ol v oh v oh v ol in-phase output voltage waveforms propagation delay times (see note d) t phz t plz 0.3 v t pzl t pzh 1.5 v 1.5 v 1.5 v 1.5 v 3 v 0 v output control (low-level enable) waveform 1 (see note b) waveform 2 (see note b) 0 v v oh v ol 3.5 v 0.3 v voltage waveforms enable and disable times, 3-state outputs notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, t r = t f 2.5 ns, duty cycle = 50%. d. the outputs are measured one at a time with one transition per measurement. e. when measuring propagation delay times of 3-state outputs, switch s1 is open. figure 9. load circuits and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-9172601m3a active lccc fk 28 1 tbd call ti level-nc-nc-nc 5962-9172601mla active cdip jt 24 1 tbd call ti level-nc-nc-nc sn74bct8244adw active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74bct8244adwe4 active soic dw 24 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74bct8244adwr active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74bct8244adwre4 active soic dw 24 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74bct8244ant active pdip nt 24 15 pb-free (rohs) cu nipdau level-nc-nc-nc sn74bct8244ante4 active pdip nt 24 15 pb-free (rohs) cu nipdau level-nc-nc-nc snj54bct8244afk active lccc fk 28 1 tbd call ti level-nc-nc-nc snj54bct8244ajt active cdip jt 24 1 tbd call ti level-nc-nc-nc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 14-nov-2005 addendum-page 1
mechanical data mcer004a january 1995 revised january 1997 post office box 655303 ? dallas, texas 75265 jt (r-gdip-t**) ceramic dual-in-line 24 leads shown 4040110/c 08/96 b 0.200 (5,08) max 0.320 (8,13) 0.290 (7,37) 0.130 (3,30) min 0.008 (0,20) 0.014 (0,36) seating plane 13 12 0.030 (0,76) 0.070 (1,78) 0.015 (0,38) min a 24 1 0.100 (2,54) max 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0 15 1.440 (37,08) 1.460 0.285 (7,39) 0.291 (36,58) (7,24) 28 pins ** 1.280 1.240 0.300 0.245 (7,62) dim b max a max a min b min (6,22) 24 (32,51) (31,50) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification. e. falls within mil std 1835 gdip3-t24, gdip4-t28, and jedec mo-058 aa, mo-058 ab
mechanical data mlcc006b october 1996 post office box 655303 ? dallas, texas 75265 fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / d 10/96 28 terminal shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold plated. e. falls within jedec ms-004
mechanical data mpdi004 october 1994 post office box 655303 ? dallas, texas 75265 nt (r-pdip-t**) plastic dual-in-line package 4040050 / b 04/95 24 pins shown 1.425 (36,20) 1.385 0.295 (7,49) (8,00) 0.315 (35,18) 28 pins ** a min a max b max b min 13 0.250 (6,35) 0.280 (7,11) 12 0.200 (5,08) max dim 24 1.230 (31,24) (32,04) 1.260 0.310 (7,87) (7,37) 0.290 b 0.125 (3,18) min seating plane 0.010 (0,25) nom a 0.070 (1,78) max 24 1 0.015 (0,38) 0.021 (0,53) 0.020 (0,51) min 0.100 (2,54) m 0.010 (0,25) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice.

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